4/12/2023 0 Comments Synopsys synplify premier 2018.3For ASIC prototypers, support for Synopsys DesignWare® Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler®. Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically. The new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of the latest release of its Synplify Pro® and Synplify® Premier FPGA synthesis tools. Extended compatibility with Synopsys' Design Compiler® tool and DesignWare® IP for a robust ASIC prototyping solution Enhanced graphical interface eases status monitoring and debugging in hierarchical design flows New Synplify® tool capabilities improve error recovery and resistance to single event upsets (SEUs), increasing reliability of FPGAs deployed in the field
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